ST STE Scanlines - Revision history

>Tomh: /* Interrupts */ Clarified: this is mainly(/entirely?) the MFP.

2020-01-16T22:45:34Z

Interrupts: Clarified: this is mainly(/entirely?) the MFP.

← Older revision		Revision as of 18:45, 16 January 2020
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	== Interrupts ==		== Interrupts ==

	The path from DE via Timer B to the 68000's interrupt input is subject to ~~both~~ a ~~latency in being signalled to the MFP and~~ in the MFP responding to the change in its input. A rule of thumb for the net signalling latency is around 28 cycles; the time to get into an interrupt routine is longer, depending in part on which instructions the 68000 is executing when the interrupt request is received.		The path from DE via Timer B to the 68000's interrupt input is subject to a substantial delay in the MFP responding to the change in its input. A rule of thumb for the net signalling latency is around 28 cycles at the 68000's clock rate; the time to get into an interrupt routine is longer, depending in part on which instructions the 68000 is executing when the interrupt request is received.

	Both vertical and horizontal sync interrupts are autovectored. On a 68000 that means that the processor will internally synchronise with its divide-by-10 E clock. In both cases a latch external to the CPU observes the transition from active to inactive; the state of the latch dictates the interrupt level presented to the CPU and the latches are cleared only by a 68000 interrupt acknowledgement. Therefore software may delay a sync interrupt arbitrarily through selection of a higher interrupt level, and they will not expire of their own volition.		Both vertical and horizontal sync interrupts are autovectored. On a 68000 that means that the processor will internally synchronise with its divide-by-10 E clock. In both cases a latch external to the CPU observes the transition from active to inactive; the state of the latch dictates the interrupt level presented to the CPU and the latches are cleared only by a 68000 interrupt acknowledgement. Therefore software may delay a sync interrupt arbitrarily through selection of a higher interrupt level, and they will not expire of their own volition.

>Tomh: "Shifter state machine" needs a lot of work, but this otherwise seeks to improve total article flow.

2020-01-15T23:05:25Z

"Shifter state machine" needs a lot of work, but this otherwise seeks to improve total article flow.

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>Tomh: Pulls horizontal state machines into a common section.

2020-01-15T18:54:40Z

Pulls horizontal state machines into a common section.

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>Tomh: Reordered to go vertical, then horizontal, then shifter. Added mention of sync interrupt latches.

2020-01-15T18:51:46Z

Reordered to go vertical, then horizontal, then shifter. Added mention of sync interrupt latches.

← Older revision		Revision as of 14:51, 15 January 2020
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	However, 820a (FREQ) is latched one cycle later than 8260 (RES); therefore relative to the timings given in this article the GLUE will always be using the value of FREQ that was true one cycle ago.		However, 820a (FREQ) is latched one cycle later than 8260 (RES); therefore relative to the timings given in this article the GLUE will always be using the value of FREQ that was true one cycle ago.

	=== ~~'Wakestates' and Phase~~ ===		== Vertical state machine ==

	~~The GLUE and the CPU start up independently when power is applied, and therefore run at an arbitrary relative phase. Each phase is common referred to as a 'wakestate'.~~

	~~Although cycle timings are given on this page, from a programmer's point of view all absolute positions are subject to a fixed offset of 0–3 cycles, set when the ST is powered on.~~

	~~Because it is a result of the power-on procedure, wakestate does not change while the ST is running or when it is reset.~~

	~~== Vertical state machine ==~~		The table below lists the times at which certain tests are applied. If a test is passed the consequence will occur shortly afterwards.

	{\| cellspacing="0" border="1" cellpadding="4"		{\| cellspacing="0" border="1" cellpadding="4"
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	== Horizontal GLUE state machine, ST ==		== Horizontal GLUE state machine, ST ==

	~~The table below lists~~ the ~~times at~~ which ~~certain tests are applied. If a test~~ is ~~passed~~ the ~~consequence will occur shortly afterwards. Where two consequences are listed, they will not occur simultaneously~~.		This model of the horizontal state machine uses an additional internal piece of information, LINE, which is set early on in the line and used to decide its total length.

	~~This model of~~ the ~~horizontal state machine uses an additional internal piece of information, LINE~~, ~~which is set early on in the line and used to decide its total length~~.		Where two consequences are listed in the table below, they will not occur simultaneously.

	{\| cellspacing="0" border="1" cellpadding="4"		{\| cellspacing="0" border="1" cellpadding="4"
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	\|HSYNC = FALSE		\|HSYNC = FALSE
	\|}		\|}

			=== Software-Observeable Latencies ===

			The path from DE via Timer B to the 68000's interrupt input is subject to both a latency in being signalled to the MFP and in the MFP responding to the change in its input. A rule of thumb for the net signalling latency is around 28 cycles; the time to get into an interrupt routine is longer, depending in part on which instructions the 68000 is executing when the interrupt request is received.

			Both vertical and horizontal sync interrupts are autovectored. On a 68000 that means that the processor will internally synchronise with its divide-by-10 E clock. In both cases a latch external to the CPU observes the transition from active to inactive; the state of the latch dictates the interrupt level presented to the CPU and the latches are cleared only by a 68000 interrupt acknowledgement. Therefore software may delay a sync interrupt arbitrarily through selection of a higher interrupt level, and they will not expire of their own volition.

			=== 'Wakestates' and Phase ===

			The GLUE and the CPU start up independently when power is applied, and therefore run at an arbitrary relative phase. Each phase is common referred to as a 'wakestate'.

			Although cycle timings are given on this page, from a programmer's point of view all absolute positions are subject to a fixed offset of 0–3 cycles, set when the ST is powered on.

			Because it is a result of the power-on procedure, wakestate does not change while the ST is running or when it is reset.

	=== Effects of Wakestate ===		=== Effects of Wakestate ===
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	The DL3-DL6 moniker in parenthesis above is another way to name the wakestates, after how long the delay is between the GLUE raising DE (Display Enable), which it does one cycle later than the checks described above, and the MMU detecting it [http://www.atari-forum.com/viewtopic.php?f=16&t=24855&start=274]. This has also the side effect of the wakestates being physically offset on screen by one pixel from eachother - WS2 (DL3) leftmost and WS1 (DL6) rightmost. This is caused by monitors using HSYNC to place the screen and depending on wakestate the distance between the HSYNC pulse and the displayed pixels differs.		The DL3-DL6 moniker in parenthesis above is another way to name the wakestates, after how long the delay is between the GLUE raising DE (Display Enable), which it does one cycle later than the checks described above, and the MMU detecting it [http://www.atari-forum.com/viewtopic.php?f=16&t=24855&start=274]. This has also the side effect of the wakestates being physically offset on screen by one pixel from eachother - WS2 (DL3) leftmost and WS1 (DL6) rightmost. This is caused by monitors using HSYNC to place the screen and depending on wakestate the distance between the HSYNC pulse and the displayed pixels differs.

	~~=== Software-Observeable Latencies ===~~

	The path from DE via Timer B to the 68000's interrupt input is subject to both a latency in reaching the MFP and in the MFP responding to the change in its input. A rule of thumb for the net signalling latency is around 28 cycles; the time to get into an interrupt routine is longer, depending in part on which instructions the 68000 is executing when the interrupt request is received.

	~~As with vertical sync, interrupts triggered by horizontal sync are autovectored. On a 68000 that means that the processor will internally synchronise with its divide-by-10 E clock.~~

	== MMU, ST ==		== MMU, ST ==

>Tomh: Removed 'necessarily' as the result touted is universal.

2020-01-15T18:44:50Z

Removed 'necessarily' as the result touted is universal.

← Older revision		Revision as of 14:44, 15 January 2020
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	== Horizontal GLUE state machine, ST ==		== Horizontal GLUE state machine, ST ==

	The table below lists the times at which certain tests are applied. If a test is passed, the consequence ~~or consequences~~ will ~~apply at a time~~ shortly afterwards. ~~They~~ will not ~~necessarily~~ occur simultaneously.		The table below lists the times at which certain tests are applied. If a test is passed the consequence will occur shortly afterwards. Where two consequences are listed, they will not occur simultaneously.

	This model of the horizontal state machine uses an additional internal piece of information, LINE, which is set early on in the line and used to decide its total length.		This model of the horizontal state machine uses an additional internal piece of information, LINE, which is set early on in the line and used to decide its total length.

>Tomh: /* Vertical state machine */ Corrects table heading.

2020-01-02T22:41:54Z

Vertical state machine: Corrects table heading.

← Older revision		Revision as of 18:41, 2 January 2020
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	!Line		!Line
	!Cycle		!Cycle
	\|Test		!Test
	!Consequence		!Consequence
	\|-		\|-

>Tomh: Pulls the vertical state machine section up to the top, rather than having it between the two horizontal state machines and the list of potential horizontal line lengths.

2020-01-02T20:09:00Z

Pulls the vertical state machine section up to the top, rather than having it between the two horizontal state machines and the list of potential horizontal line lengths.

@@ Line 6: / Line 6: @@
 Two state machines exist in the GLUE, a horizontal machine and a vertical machine. These observe the programmer-set display frequency and produce sync and blank signals appropriately. They also produce an output that indicates when pixels should appear, which is used as a trigger by the Shifter to fetch data.
 Outputs common to the two state machines are a pixels-enabled flag and signals to indicate blank and sync periods.
@@ Line 28: / Line 30: @@
 Because it is a result of the power-on procedure, wakestate does not change while the ST is running or when it is reset.
 == Horizontal GLUE state machine, ST ==
@@ Line 252: / Line 301: @@
 Todo: Describe when H becomes DE in cycles as already done for ST MMU
 == Shifter state machine ==

>Tomh: Fixed: incomplete, not complete, obviously.

2019-12-29T23:58:39Z

Fixed: incomplete, not complete, obviously.

← Older revision		Revision as of 19:58, 29 December 2019
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	This page provides pseudocode descriptions of various processes involved in the generation of each frame of the video output, in both the Atari ST and the STE.		This page provides pseudocode descriptions of various processes involved in the generation of each frame of the video output, in both the Atari ST and the STE.

	Although this page has as a goal to contain everything that's currently known, it should be considered ~~complete~~.		Although this page has as a goal to contain everything that's currently known, it should be considered incomplete.

	== Model ==		== Model ==

>Tomh: /* Horizontal GLUE state machine, ST */ Corrects column title.

2019-12-18T20:30:54Z

Horizontal GLUE state machine, ST: Corrects column title.

← Older revision		Revision as of 16:30, 18 December 2019
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	!Cycle		!Cycle
	!Test		!Test
	\|Consequence		!Consequence
	\|-		\|-
	\|4		\|4

>Tomh: Attempts a more substantial clean-up of the opening section.

2019-12-18T15:29:29Z

Attempts a more substantial clean-up of the opening section.

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